Memory transistor with multiple charge storing layers and a high work function gate electrode

ABSTRACT

An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 15/335,180, filed on Oct. 26, 2016, which is a continuation of U.S. patent application Ser. No. 14/811,346, filed Jul. 28, 2015, now U.S. Pat. No. 9,502,543, issued on Nov. 22, 2016, which is a continuation of U.S. patent application Ser. No. 14/159,315, filed on Jan. 20, 2014, now U.S. Pat. No. 9,093,318, issued on Jul. 28, 2015, which is a continuation of U.S. patent application Ser. No. 13/539,466, filed on Jul. 1, 2012, now U.S. Pat. No. 8,633,537, issued on Jan. 21, 2014, which is a continuation-in-part of patent application Ser. No. 13/288,919, filed Nov. 3, 2011, now U.S. Pat. No. 8,859,374, issued on Oct. 14, 2014, which is a divisional of U.S. patent Ser. No. 12/152,518, filed May 13, 2008, now U.S. Pat. No. 8,063,434, issued Nov. 22, 2011, which claims the benefit of priority to U.S. Provisional Patent Application No. 60/940,160, filed May 25, 2007, all of which application are hereby incorporated by reference in their entirety.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, and more particularly to integrated circuits including non-volatile semiconductor memories and methods of fabricating the same.

BACKGROUND

Non-volatile semiconductor memories are devices that can be electrically erased and reprogrammed. One type of non-volatile memory that is widely used for general storage and transfer of data in and between computers and other electronic devices is flash memory, such as a split gate flash memory. A split gate flash memory transistor has an architecture similar to that of a conventional logic transistor, such as Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), in that it also includes a control gate formed over a channel connecting a source and drain in a substrate. However, the memory transistor further includes a memory or charge trapping layer between the control gate and the channel and insulated from both by insulating or dielectric layers. A programming voltage applied to the control gate traps a charge on the charge trapping layer, partially canceling or screening an electric field from the control gate, thereby changing a threshold voltage (V_(T)) of the transistor and programming the memory cell. During read-out, this shift in V_(T) is sensed by the presence or absence of current flow through the channel with application of a predetermined read-out voltage. To erase the memory transistor, an erase voltage is applied to the control gate to restore, or reverse the shift in V_(T).

An important measure of merit for flash memories is data retention time, which is the time for which the memory transistor can hold charge or remain programmed without the application of power. The charge stored or trapped in the charge trapping layer decreases over time due to leakage current through the insulating layers, thereby reducing the difference between a programmed threshold voltage (VTP) and an erased threshold voltage (VTE) limiting data retention of the memory transistor.

One problem with conventional memory transistors and methods of forming the same is that the charge trapping layer typically has poor or decreasing data retention over time, limiting the useful transistor lifetime. Referring to FIG. 1A, if the charge trapping layer is silicon (Si) rich there is a large, initial window or difference between VTP, represented by graph or line 102, and the VTE, represented by line 104, but the window collapse very rapidly in retention mode to an end of life (EOL 106) of less than about 1.E+07 seconds.

Referring to FIG. 1B, if on the other hand the charge trapping layer is if a high quality nitride layer, that is one having a low stoichiometric concentration of Si, the rate of collapse of the window or Vt slope in retention mode is reduced, but the initial program-erase window is also reduced. Moreover, the slope of Vt in retention mode is still appreciably steep and the leakage path is not sufficiently minimized to significantly improve data retention, thus EOL 106 is only moderately improved.

Another problem is that increasingly semiconductor memories combine logic transistors, such as MOSFET's, with memory transistors in integrated circuits (ICs) fabricated on a common substrate for embedded memory or System-On-Chip (SOC) applications. Many of the current processes for forming performance of memory transistors are incompatible with those used for fabricating logic transistors.

Accordingly, there is a need for memory transistors and methods of forming the same that provides improved data retention and increased transistor lifetime. It is further desirable that the methods of forming the memory device are compatible with those for forming logic elements in the same IC formed on a common substrate.

SUMMARY OF THE INVENTION

The present invention provides a solution to these and other problems, and offers further advantages over conventional memory cells or devices and methods of fabricating the same.

Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the ONNO stack. In one embodiment, the ONNO stack includes a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer. In another embodiment, the multi-layer charge-trapping region further includes an oxide anti-tunneling layer separating the first nitride layer from the second nitride layer.

BRIEF DESCRIPTION OF THE DRAWINGS

These and various other features and advantages of the present invention will be apparent upon reading of the following detailed description in conjunction with the accompanying drawings and the appended claims provided below, where:

FIG. 1A is a graph showing data retention for a memory transistor using a charge storage layer formed according to a conventional method and having a large initial difference between programming and erase voltages but which loses charge quickly;

FIG. 1B is a graph showing data retention for a memory transistor using a charge storage layer formed according to a conventional method and having a smaller initial difference between programming and erase voltages;

FIGS. 2A through 2D are partial cross-sectional side views of a semiconductor device illustrating a process flow for forming a semiconductor device including a logic transistor and non-volatile memory transistor according to an embodiment of the present invention;

FIG. 3 is a partial cross-sectional side view of a semiconductor device including a logic transistor and non-volatile memory transistor comprising high work function gate electrodes according to an embodiment of the present invention;

FIGS. 4A and 4B illustrates a cross-sectional view of a non-volatile memory device including an ONONO stack;

FIG. 5 depicts a flowchart representing a series of operations in a method for fabricating a non-volatile charge trap memory device including an ONONO stack, in accordance with an embodiment of the present invention;

FIG. 6A illustrates a non-planar multigate device including a multi-layer charge-trapping region;

FIG. 6B illustrates a cross-sectional view of the non-planar multigate device of FIG. 6A;

FIGS. 7A and 7B illustrate a non-planar multigate device including a multi-layer charge-trapping region and a horizontal nanowire channel;

FIG. 7C illustrates a cross-sectional view of a vertical string of non-planar multigate devices of FIG. 7A;

FIGS. 8A and 8B illustrate a non-planar multigate device including a multi-layer charge-trapping region and a vertical nanowire channel;

FIGS. 9A through 9F illustrate a gate first scheme for fabricating the non-planar multigate device of FIG. 8A; and

FIGS. 10A through 10F illustrate a gate last scheme for fabricating the non-planar multigate device of FIG. 8A.

DETAILED DESCRIPTION

The present invention is directed generally to non-volatile memory transistor including a multi-layer charge storage layer and high work function gate electrode to increase data retention and/or to improve programming time and efficiency. The structure and method are particularly useful for embedded memory or System-On-Chip (SOC) applications in which a semiconductor device includes both a logic transistor and non-volatile memory transistor comprising high work function gate electrodes formed on a common substrate.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description.

Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term “to couple” as used herein may include both to directly connect and to indirectly connect through one or more intervening components.

Briefly, a non-volatile memory transistor according to the present invention includes a high work function gate electrode formed over an oxide-nitride-oxide (ONO) dielectric stack. By high work function gate electrode it is meant that the minimum energy needed to remove an electron from the gate electrode is increased.

In certain preferred embodiments, the high work function gate electrode comprises a doped polycrystalline silicon or polysilicon (poly) layer, the fabrication of which can be can be readily integrated into standard complementary metal-oxide-semiconductor (CMOS) process flows, such as those used fabricate metal-oxide-semiconductor (MOS) logic transistors, to enable fabrication of semiconductor memories or devices including both memory and logic transistors. More preferably, the same doped polysilicon layer can also be patterned to form a high work function gate electrode for the MOS logic transistor, thereby improving the performance of the logic transistor and increasing the efficiency of the fabrication process. Optionally, the ONO dielectric stack includes a multi-layer charge storage or charge trapping layer to further improve performance, and in particular data retention, of the memory transistor.

A semiconductor device including a non-volatile memory transistor comprising a high work function gate electrode and methods of forming the same will now be described in detail with reference to FIGS. 2A through 2D, which are partial cross-sectional side views of intermediate structures illustrating a process flow for forming a semiconductor device including both memory and logic transistors. For purposes of clarity, many of the details of semiconductor fabrication that are widely known and are not relevant to the present invention have been omitted from the following description.

Referring to FIG. 2 , fabrication of the semiconductor device begins with formation of an ONO dielectric stack 202 over a surface 204 of a wafer or substrate 206. Generally, the ONO dielectric stack 202 includes a thin, lower oxide layer or tunneling oxide layer 208 that separates or electrically isolates a charge trapping or storage layer 210 from a channel region (not shown) of the memory transistor in the substrate 206, and a top or blocking oxide layer 212. Preferably, as noted above and as shown in FIGS. 2A-2D, the charge storage layer 210 is a multi-layer charge storage layer including at least a top, charge trapping oxynitride layer 210A and a lower, substantially trap free oxynitride layer 210B.

Generally, the substrate 206 may include any known silicon-based semiconductor material including silicon, silicon-germanium, silicon-on-insulator, or silicon-on-sapphire substrate. Alternatively, the substrate 206 may include a silicon layer formed on a non-silicon-based semiconductor material, such as gallium-arsenide, germanium, gallium-nitride, or aluminum-phosphide. Preferably, the substrate 206 is a doped or undoped silicon substrate.

The lower oxide layer or tunneling oxide layer 208 of the ONO dielectric stack 202 generally includes a relatively thin layer of silicon dioxide (SiO₂) of from about 15 angstrom (Å) to about 22 Å, and more preferably about 18 Å. The tunneling oxide layer 208 can be formed or deposited by any suitable means including, for example, being thermally grown or deposited using chemical vapor deposition (CVD). In a preferred embodiment, the tunnel dielectric layer is formed or grown using a steam anneal. Generally, the process includes a wet-oxidizing method in which the substrate 206 is placed in a deposition or processing chamber, heated to a temperature from about 700° C. to about 850° C., and exposed to a wet vapor for a predetermined period of time selected based on a desired thickness of the finished tunneling oxide layer 208. Exemplary process times are from about 5 to about 20 minutes. The oxidation can be performed at atmospheric or at low pressure.

In a preferred embodiment, the oxynitride layers 210A, 210B, of the multi-layer charge storage layer 210 are formed or deposited in separate steps utilizing different processes and process gases or source materials, and have an overall or combined thickness of from about 70 Å to about 150 Å, and more preferably about 100 Å. The lower, trap free oxynitride layer 210B can be formed or deposited by any suitable means including, for example, deposition in a low pressure CVD process using a process gas including a silicon source, such as silane (SiH₄), chlorosilane (SiH₃Cl), dichlorosilane (SiH₂Cl₂), tetrachlorosilane (SiCl₄), a nitrogen source, such as nitrogen (N₂), ammonia (NH₃), nitrogen trioxide (NO₃) or nitrous oxide (N₂O), and an oxygen-containing gas, such as oxygen (O₂) or N₂O. In one embodiment the trap free oxynitride layer 210B is deposited in a low pressure CVD process using a process gas including dichlorosilane, NH₃ and N₂O, while maintaining the chamber at a pressure of from about 5 millitorr (mT) to about 500 mT, and maintaining the substrate at a temperature of from about 700° C. to about 850° C. and more preferably at least about 780° C., for a period of from about 2.5 minutes to about 20 minutes. In particular, the process gas can include a first gas mixture of N₂O and NH₃ mixed in a ratio of from about 8:1 to about 1:8 and a second gas mixture of DCS and NH₃ mixed in a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate of from about 5 to about 200 standard cubic centimeters per minute (sccm).

The top, charge trapping oxynitride layer 210A can be deposited over the bottom oxynitride layer 210B in a CVD process using a process gas including Bis-TertiaryButylAminoSilane (BTBAS). It has been found that the use of BTBAS increases the number of deep traps formed in the oxynitride by increasing the carbon level in the charge trapping oxynitride layer 210A. Moreover, these deep traps reduce charge losses due to thermal emission, thereby further improving data retention. More preferably, the process gas includes BTBAS and ammonia (NH₃) mixed at a predetermined ratio to provide a narrow band gap energy level in the oxynitride charge trapping layer. In particular, the process gas can include BTBAS and NH₃ mixed in a ratio of from about 7:1 to about 1:7. For example, in one embodiment the charge trapping oxynitride layer 210A is deposited in a low pressure CVD process using BTBAS and ammonia NH₃ at a chamber pressure of from about 5 mT to about 500 mT, and at a substrate temperature of from about 700° C. to about 850° C. and more preferably at least about 780° C., for a period of from about 2.5 minutes to about 20 minutes.

It has been found that an oxynitride layer produced or deposited under the above conditions yields a trap-rich oxynitride layer 210A, which improves the program and erase speed and increases of the initial difference (window) between program and erase voltages without compromising a charge loss rate of the memory transistor, thereby extending the operating life (EOL) of the device. Preferably, the charge trapping oxynitride layer 210A has a charge trap density of at least about 1E10/cm², and more preferably from about 1E12/cm² to about 1E14/cm².

Alternatively, the charge trapping oxynitride layer 210A can be deposited over the bottom oxynitride layer 210B in a CVD process using a process gas including BTBAS and substantially not including ammonia (NH₃). In this alternative embodiment of the method, the step of depositing the top, charge trapping oxynitride layer 210A is followed by a thermal annealing step in a nitrogen atmosphere including nitrous oxide (N₂O), NH₃, and/or nitrogen oxide (NO).

Preferably, the top, charge trapping oxynitride layer 210A is deposited sequentially in the same CVD tool used to form the bottom, trap free oxynitride layer 210B, substantially without breaking vacuum on the deposition chamber. More preferably, the charge trapping oxynitride layer 210A is deposited substantially without altering the temperature to which the substrate 206 was heated during deposition of the trap free oxynitride layer 210B.

A suitable thickness for the lower, trap free oxynitride layer 210B has been found to be from about 10 Å to about 80 Å, and a ratio of thicknesses between the bottom layer and the top, charge trapping oxynitride layer has been found to be from about 1:6 to about 6:1, and more preferably at least about 1:4.

The top oxide layer 212 of the ONO dielectric stack 202 includes a relatively thick layer of SiO₂ of from about 20 Å to about 70 Å, and more preferably about 45 Å. The top oxide layer 212 can be formed or deposited by any suitable means including, for example, being thermally grown or deposited using CVD. In a preferred embodiment, the top oxide layer 212 is a high-temperature-oxide (HTO) deposited using CVD process. Generally, the deposition process includes exposing the substrate 306 to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as O₂ or N₂O in a deposition chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650° C. to about 850° C.

Preferably, the top oxide layer 212 is deposited sequentially in the same tool used to form the oxynitride layers 210A, 210B. More preferably, the oxynitride layers 210A, 210B, and the top oxide layer 212 are formed or deposited in the same tool used to grow the tunneling oxide layer 208. Suitable tools include, for example, an ONO AVP, commercially available from AVIZA technology of Scotts Valley, Calif.

Referring to FIG. 2B, in those embodiments in which the semiconductor device is to further include a logic transistor, such as a MOS logic transistor, formed on the surface of the same substrate the ONO dielectric stack 202 is removed from a region or area of the surface 204 in which the logic transistor is to be formed, and an oxide layer 214 the formed thereon.

Generally, the ONO dielectric stack 202 is removed from the desired region or area of the surface 204 using standard photolithographic and oxide etch techniques. For example, in one embodiment a patterned mask layer (not shown) is formed from a photo-resist deposited on the ONO dielectric stack 202, and the exposed region etched or removed using a low pressure radiofrequency (RF) coupled or generated plasma comprising fluorinated hydrocarbon and/or fluorinated carbon compounds, such as C₂H₂F₄ commonly referred to as Freon®. Generally, the processing gas further includes argon (Ar) and nitrogen (N₂) at flow rates selected to maintain a pressure in the etch chamber of from about 50 mT to about 250 mT during processing.

The oxide layer 214 of the logic transistor can include a layer of SiO₂ having a thickness of from about 30 to about 70 Å, and can be thermally grown or deposited using CVD. In one embodiment, the oxide layer 214 is thermally grown using a steam oxidation process, for example, by maintaining the substrate 206 in a steam atmosphere at a temperature of from about 650° C. to about 850° C. for a period of from about 10 minutes to about 120 minutes.

Next, a doped polysilicon layer is formed on a surface of the ONO dielectric stack 202 and, preferably, the oxide layer 214 of the logic transistor. More preferably, the substrate 206 is a silicon substrate or has a silicon surface on which the ONO dielectric stack is formed to form a silicon-oxide-nitride-oxide-silicon (SONOS) gate stack of a SONOS memory transistor.

Referring to FIG. 2C, forming of the doped polysilicon layer begins with the deposition of a conformal polysilicon layer 216 having a thickness of from about 200 Å to about 2000 Å over the ONO dielectric stack 202 and the oxide layer 214. The polysilicon layer 216 can be formed or deposited by any suitable means including, for example, deposition in a low pressure CVD process using a silicon source or precursor. In one embodiment the polysilicon layer 216 is deposited in a low pressure CVD process using a silicon containing process gas, such as silane or dichlorosilane, and N₂, while maintaining the substrate 206 in a chamber at a pressure of from about 5 to 500 mT, and at a temperature of from about 600° C. to about 1000° C. for a period of from about 20 minutes to about 100 minutes to a substantially undoped polysilicon layer. The polysilicon layer 216 can be formed or grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane or difluoroborane (BF₂) to the CVD chamber during the low pressure CVD process.

In one embodiment, the polysilicon layer 216 is doped following the growth or formation in the LPCVD process using ion implantation process. For example, the polysilicon layer 216 can be doped by implanting boron (B⁺) or BF₂ ions at an energy of from about 5 to about 100 kilo-electron volts (keV), and a dose of from about 1e14 cm⁻² to about 1e16 cm⁻² to form an N-type (NMOS) SONOS memory transistor and, preferably, a P-type (PMOS) logic transistor having high work function gate electrodes. More preferably, the polysilicon layer 216 is doped to a concentration or dose selected so that the minimum energy needed to remove an electron from the gate electrode is from at least about 4.8 electron volts (eV) to about 5.3 eV.

Alternatively, the polysilicon layer 216 can be doped by ion implantation after patterning or etching the polysilicon layer and the underlying dielectric layers. It will be appreciated that this embodiment includes additional masking steps to protect exposed areas of the substrate 206 surface 204 and/or the dielectric layers from receiving undesired doping. However, generally such a masking step is included in existing process flows regardless of whether the implantation occurs before or after patterning.

Referring to FIG. 2D, the polysilicon layer 216 and the underlying dielectric stack 202 and oxide layer 214 are patterned or etched to form high work function gate electrodes 218 of the memory transistor 220 and logic transistor 222. In one embodiment polysilicon layer 216 can be etched or patterned using a plasma comprising hydrobromic acid (HBr), chlorine (CL₂) and/or oxygen (O₂) at a pressure of about 25 mTorr, and a power of about 450 W. The oxide layers 208, 212, 214, and oxynitride layers 210A, 210B, can be etched using standard photolithographic and oxide etch techniques as described. For example, in one embodiment the patterned polysilicon layer 216 is used as a mask, and the exposed oxide layers 208, 212, 214, and oxynitride layers 210A, 210B, etched or removed using low pressure RF plasma. Generally, the plasma is formed from a processing gas comprising a fluorinated hydrocarbon and/or fluorinated carbon compounds, and further including Ar and N₂ at flow rates selected to maintain a pressure in the etch chamber of from about 50 mT to about 250 mT during processing.

Finally, the substrate is thermal annealed with a single or multiple annealing steps at a temperature of from about 800° C. to about 1050° C. for a time of from about 1 second to about 5 minutes to drive in ions implanted in the polysilicon layer 216, and to repair damage to the crystal structure of the polysilicon layer caused by ion implantation. Alternatively, advanced annealing techniques, such as flash and laser, can be employed with temperatures as high as 1350° C. and anneal times as low as 1 millisecond.

A partial cross-sectional side view of a semiconductor device 300 including a logic transistor 302 and non-volatile memory transistor 304 comprising high work function gate electrodes according to an embodiment of the present invention is shown in FIG. 3 . Referring to FIG. 3 , the memory transistor 304 is formed on a silicon substrate 306 and comprises a high work function gate electrode 308 formed from a doped polysilicon layer overlying a dielectric stack 310. The dielectric stack 310 overlies and controls current through a channel region 312 separating heavily doped source and drain (S/D) regions 314. Preferably, the dielectric stack 310 includes a tunnel dielectric layer 316, a multi-layer charge storage layer 318A, 318B, and a top or blocking oxide layer 320. More preferably, the multi-layer charge storage layer 318A, 318B, includes at least a top, charge trapping oxynitride layer 318A and a lower, substantially trap free oxynitride layer 318B. Optionally, as shown in FIG. 3 , the memory transistor 304 further includes one or more sidewall spacers 322 surrounding the gate stack to electrically insulate it from contacts (not shown) to the S/D regions 320 and from other transistors in the semiconductor device formed on the substrate 306.

The logic transistor 302 comprises a gate electrode 324 overlying an oxide layer 326 formed over a channel region 328 separating heavily doped source and drain regions 330, and, optionally, can include one or more sidewall spacers 332 surrounding the gate electrically insulate it from contacts (not shown) to the S/D regions. Preferably, as shown in FIG. 3 , the gate electrode 324 of the logic transistor 302 also comprises a high work function gate electrode formed from a doped polysilicon layer.

Generally, the semiconductor device 300 further includes a number of isolation structures 334, such as a local oxidation of silicon (LOCOS) region or structure, a field oxidation region or structure (FOX), or a shallow trench isolation (STI) structure to electrically isolate individual transistors formed on the substrate 306 from one another.

Implementations and Alternatives

In one aspect the present disclosure is directed to semiconductor devices including memory transistors with a high work function gate electrode and a multi-layer charge-trapping region. FIG. 4A is a block diagram illustrating a cross-sectional side view of an embodiment of one such memory transistor 400. The memory transistor 400 includes a ONNO stack 402 including an ONNO structure 404 formed over a surface 406 of a substrate 408. Substrate 408 includes one or more diffusion regions 410, such as source and drain regions, aligned to the gate stack 402 and separated by a channel region 412. Generally, the ONNO stack 402 includes a high work function gate electrode 414 formed upon and in contact with the ONNO structure 404. The high work function gate electrode 414 is separated or electrically isolated from the substrate 408 by the ONNO structure 404. The ONNO structure 404 includes a thin, lower oxide layer or tunnel dielectric layer 416 that separates or electrically isolates the ONNO stack 402 from the channel region 412, a top or blocking dielectric layer 420, and a multi-layer charge-trapping region 422.

The nanowire channel region 412 can comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel region. Optionally, where the channel region 412 includes a crystalline silicon, the channel region can be formed to have <100> surface crystalline orientation relative to a long axis of the channel region.

The high work function gate electrode 414 includes a doped polysilicon layer formed or deposited in a low pressure CVD process and having a thickness of from about 200 Å to about 2000 Å. As noted above, the polysilicon layer of the high work function gate electrode 414 can be formed or grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane or difluoroborane (BF₂) to the CVD chamber during the low pressure CVD process, or can be doped following the growth or formation in the CVD process using an ion implantation process. In either embodiment, the polysilicon layer of the high work function gate electrode 414 is doped to a concentration or dose selected so that the minimum energy needed to remove an electron from the gate electrode is from at least about 4.8 electron volts (eV) to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 414 is doped by implanting boron (B⁺) or BF₂ ions at an energy of from about 5 to about 100 kilo-electron volts (keV), and a dose of from about 1e14 cm⁻² to about 1e16 cm⁻² form an N-type (NMOS) memory transistor.

The tunnel dielectric layer 416 may be any material and have any thickness suitable to allow charge carriers to tunnel into the multi-layer charge-trapping region 422 under an applied gate bias while maintaining a suitable barrier to leakage when the memory transistor 400 is unbiased. In one embodiment, the tunnel dielectric layer 416 is formed by a thermal oxidation process and is composed of silicon dioxide or silicon oxy-nitride, or a combination thereof. In another embodiment, the tunnel dielectric layer 416 is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) and is composed of a dielectric layer which may include, but is not limited to, silicon nitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide. In a specific embodiment, the tunnel dielectric layer 416 has a thickness in the range of 1-10 nanometers. In a particular embodiment, the tunnel dielectric layer 416 has a thickness of approximately 2 nanometers.

In one embodiment, the blocking dielectric layer 420 comprises a high temperature oxide (HTO). The higher quality HTO oxide enables the blocking dielectric layer 420 to be scaled in thickness. In an exemplary embodiment, the thickness of the blocking dielectric layer 420 comprising a HTO oxide is between 2.5 nm and 10.0 nm.

In another embodiment, the blocking dielectric layer 420 is further modified to incorporate nitrogen. In one such embodiment, the nitrogen is incorporated in the form of an ONO stack across the thickness of the blocking dielectric layer 420. Such a sandwich structure in place of the conventional pure oxygen blocking dielectric layer advantageously reduces the EOT of the entire stack 402 between the channel region 412 and high work function gate electrode 414 as well as enable tuning of band offsets to reduce back injection of carriers. The ONO stack blocking dielectric layer 420 can then be incorporated with the tunnel dielectric layer 416 and the multi-layer charge trapping layer 422 comprising an oxygen-rich first nitride layer 422 a, an oxygen-lean second nitride layer 422 b and an anti-tunneling layer 422 c.

The multi-layer charge-trapping region 422 generally includes at least two nitride layers having differing compositions of silicon, oxygen and nitrogen, including an oxygen-rich, first nitride layer 422 a, and a silicon-rich, nitrogen-rich, and oxygen-lean second nitride layer 422 b, a silicon-rich. In some embodiments, such as that shown in FIG. 4B, the multi-layer charge-trapping region further includes an anti-tunneling layer 422 c comprising an oxide, such as silicon dioxide, separating the oxygen-lean second nitride layer 422 b from the oxygen-rich, first nitride layer 422 a, to provide a ONONO stack 402 including an ONONO structure 404.

It has been found that an oxygen-rich, first nitride layer 422 a decreases the charge loss rate after programming and after erase, which is manifested in a small voltage shift in the retention mode, while a silicon-rich, nitrogen-rich, and oxygen-lean second nitride layer 422 b improves the speed and increases of the initial difference between program and erase voltage without compromising a charge loss rate of memory transistors made using an embodiment of the silicon-oxide-oxynitride-oxide-silicon structure, thereby extending the operating life of the device.

It has further been found the anti-tunneling layer 422 c substantially reduces the probability of electron charge that accumulates at the boundaries of the oxygen-lean second nitride layer 422 b during programming from tunneling into the first nitride layer 422 a, resulting in lower leakage current than for a conventional non-volatile memory transistor.

The multi-layer charge-trapping region can have an overall thickness of from about 50 Å to about 150 Å, and in certain embodiments less than about 100 Å, with the with the thickness of the anti-tunneling layer 422 c being from about 5 Å to about 20 Å, and the thicknesses of the nitride layers 404 b, 404 a, being substantially equal.

A method or forming or fabricating a semiconductor device including a memory transistor with a high work function gate electrode and a multi-layer charge-trapping region according to one embodiment will now be described with reference to the flowchart of FIG. 5 .

Referring to FIG. 5 , the method begins with forming a tunnel dielectric layer, such as a first oxide layer, over a silicon containing layer on a surface of a substrate (500). The tunnel dielectric layer can be formed or deposited by any suitable means, including a plasma oxidation process, In-Situ Steam Generation (ISSG) or a radical oxidation process. In one embodiment, the radical oxidation process involves flowing hydrogen (H₂) and oxygen (O₂) gas into a processing chamber or furnace to effect growth of a the tunnel dielectric layer by oxidation consumption of a portion of the substrate.

Next, an oxygen-rich first nitride layer of the multi-layer charge-trapping region is formed on a surface of the tunnel dielectric layer (502). In one embodiment, the oxygen-rich first nitride layer is formed or deposited in a low pressure CVD process using a silicon source, such as silane (SiH₄), chlorosilane (SiH₃Cl), dichlorosilane or DCS (SiH₂Cl₂), tetrachlorosilane (SiCl₄) or Bis-TertiaryButylAmino Silane (BTBAS), a nitrogen source, such as nitrogen (N₂), ammonia (NH₃), nitrogen trioxide (NO₃) or nitrous oxide (N₂O), and an oxygen-containing gas, such as oxygen (O₂) or N₂O. Alternatively, gases in which hydrogen has been replaced by deuterium can be used, including, for example, the substitution of deuterated-ammonia (ND₃) for NH₃. The substitution of deuterium for hydrogen advantageously passivates Si dangling bonds at the silicon-oxide interface, thereby increasing an NBTI (Negative Bias Temperature Instability) lifetime of the devices.

For example, the lower or oxygen-rich first nitride layer can be deposited over the tunnel dielectric layer by placing the substrate in a deposition chamber and introducing a process gas including N₂O, NH₃ and DCS, while maintaining the chamber at a pressure of from about 5 milliTorr (mT) to about 500 mT, and maintaining the substrate at a temperature of from about 700 degrees Celsius to about 850 degrees Celsius and in certain embodiments at least about 760 degrees Celsius, for a period of from about 2.5 minutes to about 20 minutes. In particular, the process gas can include a first gas mixture of N₂O and NH₃ mixed in a ratio of from about 8:1 to about 1:8 and a second gas mixture of DCS and NH₃ mixed in a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate of from about 5 to about 200 standard cubic centimeters per minute (sccm). It has been found that an oxynitride layer produced or deposited under these condition yields a silicon-rich, oxygen-rich first nitride layer.

Next, an anti-tunneling layer is formed or deposited on a surface of the first nitride layer (504). As with the tunnel dielectric layer, the anti-tunneling layer can be formed or deposited by any suitable means, including a plasma oxidation process, In-Situ Steam Generation (ISSG) or a radical oxidation process. In one embodiment, the radical oxidation process involves flowing hydrogen (H₂) and oxygen (O₂) gas into a batch-processing chamber or furnace to effect growth of the anti-tunneling layer by oxidation consumption of a portion of the first nitride layer.

The top or oxygen-lean second nitride layer of the multi-layer charge-trapping region is then formed on a surface of the anti-tunneling layer (506). The oxygen-lean second nitride layer can be deposited over the anti-tunneling layer in a CVD process using a process gas including N₂O, NH₃ and DCS, at a chamber pressure of from about 5 mT to about 500 mT, and at a substrate temperature of from about 700 degrees Celsius to about 850 degrees Celsius and in certain embodiments at least about 760 degrees Celsius, for a period of from about 2.5 minutes to about 20 minutes. In particular, the process gas can include a first gas mixture of N₂O and NH₃ mixed in a ratio of from about 8:1 to about 1:8 and a second gas mixture of DCS and NH₃ mixed in a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate of from about 5 to about 20 sccm. It has been found that a nitride layer produced or deposited under these condition yields a silicon-rich, nitrogen-rich, and oxygen-lean second nitride layer, which improves the speed and increases of the initial difference between program and erase voltage without compromising a charge loss rate of memory transistors made using an embodiment of the silicon-oxide-oxynitride-oxide-silicon structure, thereby extending the operating life of the device.

In some embodiments, the oxygen-lean second nitride layer can be deposited over the anti-tunneling layer in a CVD process using a process gas including BTBAS and ammonia (NH₃) mixed at a ratio of from about 7:1 to about 1:7 to further include a concentration of carbon selected to increase the number of traps therein. The selected concentration of carbon in the second oxynitride layer can include a carbon concentration of from about 5% to about 15%.

Next, a top, blocking oxide layer or blocking dielectric layer is formed on a surface of the oxygen-lean second nitride layer of the multi-layer charge-trapping region (508). As with the tunnel dielectric layer and the anti-tunneling layer the blocking dielectric layer can be formed or deposited by any suitable means, including a plasma oxidation process, In-Situ Steam Generation (ISSG) or a radical oxidation process. In one embodiment, the blocking dielectric layer comprises a high-temperature-oxide (HTO) deposited using CVD process. Generally, the deposition process includes exposing the substrate 306 to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as O₂ or N₂O in a deposition chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650° C. to about 850° C.

Alternatively, the blocking dielectric layer is formed using an ISSG oxidation process. In one embodiment, the ISSG is performed in an RTP chamber, such as the ISSG chamber from Applied Materials described above, at pressures of from about 8 to 12 Torr and a temperature of about 1050° C. with an oxygen rich gas mixture hydrogen to which from about 0.5% to 33% hydrogen has been added.

It will be appreciated that in either embodiment the thickness of the second nitride layer may be adjusted or increased as some of the oxygen-lean second nitride layer will be effectively consumed or oxidized during the process of forming the blocking dielectric layer.

Finally, a high work function gate electrode is formed upon and in contact with the blocking dielectric layer (510). The high work function gate electrode includes a doped polysilicon layer formed or deposited in a low pressure CVD process and having a thickness of from about 200 Å to about 2000 Å. As noted above, the polysilicon layer of the high work function gate electrode can be formed or grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane or difluoroborane (BF₂) to the CVD chamber during the low pressure CVD process, or can be doped following the growth or formation in the CVD process using an ion implantation process. In either embodiment, the polysilicon layer of the high work function gate electrode is doped to a concentration or dose selected so that the minimum energy needed to remove an electron from the gate electrode is from at least about 4.8 electron volts (eV) to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode is doped by implanting boron (B⁺) or BF₂ ions at an energy of from about 5 to about 100 kilo-electron volts (keV), and a dose of from about 1e14 cm⁻² to about 1e16 cm⁻² to form an N-type (NMOS) memory transistor.

With the completion of the gate stack fabrication, further processing may occur as known in the art to conclude fabrication of a SONOS-type memory device.

In another aspect the present disclosure is also directed to multigate or multigate-surface memory transistors including charge-trapping regions overlying two or more sides of a channel region formed on or above a surface of a substrate, and methods of fabricating the same. Multigate devices include both planar and non-planar devices. A planar multigate device (not shown) generally includes a double-gate planar device in which a number of first layers are deposited to form a first gate below a subsequently formed channel region, and a number of second layers are deposited thereover to form a second gate. A non-planar multigate device generally includes a horizontal or vertical channel region formed on or above a surface of a substrate and surrounded on three or more sides by a gate.

FIG. 6A illustrates one embodiment of a non-planar multigate memory transistor including with a high work function gate electrode. Referring to FIG. 6A, the memory transistor 600, commonly referred to as a finFET, includes a channel region 602 formed from a thin film or layer of semiconducting material overlying a surface 604 on a substrate 606 connecting a source region 608 and a drain region 610 of the memory transistor. The channel region 602 is enclosed on three sides by a fin which forms a gate 612 of the device. The thickness of the gate 612 (measured in the direction from source region to drain region) determines the effective channel region length of the device. As with the embodiments described above, the channel region 602 can comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel region. Optionally, where the channel region 602 includes a crystalline silicon, the channel region can be formed to have <100> surface crystalline orientation relative to a long axis of the channel region.

In accordance with the present disclosure, the non-planar multigate memory transistor 600 of FIG. 6A can include a high work function gate electrode and a multi-layer charge-trapping region. FIG. 6B is a cross-sectional view of a portion of the non-planar memory transistor of FIG. 6A including a portion of the substrate 606, channel region 602 and the gate 612 illustrating a high work function gate electrode 614 and a multi-layer charge-trapping region 616. The gate 612 further includes a tunnel dielectric layer 618 overlying a raised channel region 602, and a blocking dielectric layer 620 overlying the blocking dielectric layer to form a control gate of the memory transistor 600. The channel region 602 and gate 612 can be formed directly on substrate 606 or on an insulating or dielectric layer 622, such as a buried oxide layer, formed on or over the substrate.

As with the embodiments described above, the high work function gate electrode 614 includes a doped polysilicon layer formed or deposited in a low pressure CVD process and having a thickness of from about 200 Å to about 2000 Å. The polysilicon layer of the high work function gate electrode 614 can be formed or grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane or BF₂, and is doped to a concentration or dose selected so that the minimum energy needed to remove an electron from the gate electrode is from at least about 4.8 eV to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 614 is doped to a concentration of from about 1e14 cm⁻² to about 1e16 cm⁻³.

Referring to FIG. 6B, the multi-layer charge-trapping region 616 includes at least one lower or bottom oxygen-rich first nitride layer 616 a including nitride closer to the tunnel dielectric layer 618, and an upper or top oxygen-lean second nitride layer 616 b overlying the oxygen-rich first nitride layer. Generally, the oxygen-lean second nitride layer 616 b includes a silicon-rich, oxygen-lean nitride layer and includes a majority of a charge traps distributed in the multi-layer charge-trapping region, while the oxygen-rich first nitride layer 616 a includes an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the oxygen-lean second nitride layer to reduce the number of charge traps therein. By oxygen-rich it is meant wherein a concentration of oxygen in the oxygen-rich first nitride layer 616 a is from about 15 to about 40%, whereas a concentration of oxygen in oxygen-lean second nitride layer 616 b is less than about 5%.

In one embodiment, the blocking dielectric 620 also includes an oxide, such as an HTO, to provide an ONNO structure. The channel region 602 and the overlying ONNO structure can be formed directly on a silicon substrate 606 and overlaid with a high work function gate electrode 614 to provide a SONNOS structure.

In some embodiments, such as that shown in FIG. 6B, the multi-layer charge-trapping region 616 further includes at least one thin, intermediate or anti-tunneling layer 616 c including a dielectric, such as an oxide, separating the oxygen-lean second nitride layer 616 b from the oxygen-rich first nitride layer 616 a. As noted above, the anti-tunneling layer 616 c substantially reduces the probability of electron charge that accumulates at the boundaries of the oxygen-lean second nitride layer 616 b during programming from tunneling into the first nitride layer 616 a.

As with the embodiments described above, either or both of the oxygen-rich first nitride layer 616 a and the oxygen-lean second nitride layer 616 b can include silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N₂O/NH₃ and DCS/NH₃ gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. The second nitride layer of the multi-layer charge storing structure is then formed on the middle oxide layer. The oxygen-lean second nitride layer 616 b has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the oxygen-rich first nitride layer 616 a, and may also be formed or deposited by a CVD process using a process gas including DCS/NH₃ and N₂O/NH₃ gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer.

In those embodiments including an intermediate or anti-tunneling layer 616 c including oxide, the anti-tunneling layer can be formed by oxidation of the bottom oxynitride layer, to a chosen depth using radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1000-1100 degrees Celsius using a single wafer tool, or 800-900 degrees Celsius using a batch reactor tool. A mixture of H₂ and O₂gasses may be employed at a pressure of 300-500 Tor for a batch process, or 10-15 Tor using a single vapor tool, for a time of 1-2 minutes using a single wafer tool, or 30 min-1 hour using a batch process.

Finally, in those embodiments including a blocking dielectric 620 including oxide the oxide may be formed or deposited by any suitable means. In one embodiment the oxide of the blocking dielectric 620 is a high temperature oxide deposited in a HTO CVD process. Alternatively, the blocking dielectric 620 or blocking oxide layer may be thermally grown, however it will be appreciated that in this embodiment the top nitride thickness may be adjusted or increased as some of the top nitride will be effectively consumed or oxidized during the process of thermally growing the blocking oxide layer. A third option is to oxidize the second nitride layer to a chosen depth using radical oxidation.

A suitable thickness for the oxygen-rich first nitride layer 616 a may be from about 30 Å to about 160 Å (with some variance permitted, for example ±10 A), of which about 5-20 Å may be consumed by radical oxidation to form the anti-tunneling layer 616 c. A suitable thickness for the oxygen-lean second nitride layer 616 b may be at least 30 Å. In certain embodiments, the oxygen-lean second nitride layer 616 b may be formed up to 130 Å thick, of which 30-70 Å may be consumed by radical oxidation to form the blocking dielectric 620. A ratio of thicknesses between the oxygen-rich first nitride layer 616 a and oxygen-lean second nitride layer 616 b is approximately 1:1 in some embodiments, although other ratios are also possible.

In other embodiments, either or both of the oxygen-lean second nitride layer 616 b and the blocking dielectric 620 may include a high K dielectric. Suitable high K dielectrics include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y₂O₃.

In another embodiment, shown in FIGS. 7A and 7B, the memory transistor can include a nanowire channel region formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source region and a drain region of the memory transistor. By nanowire channel region it is meant a conducting channel region formed in a thin strip of crystalline silicon material, having a maximum cross-sectional dimension of about 10 nanometers (nm) or less, and more preferably less than about 6 nm.

Referring to FIG. 7A, the memory transistor 700 includes a horizontal nanowire channel region 702 formed from a thin film or layer of semiconducting material on or overlying a surface on a substrate 706, and connecting a source region 708 and a drain region 710 of the memory transistor. In the embodiment shown, the device has a gate-all-around (GAA) structure in which the nanowire channel region 702 is enclosed on all sides by a gate 712 of the device. The thickness of the gate 712 (measured in the direction from source region to drain region) determines the effective channel region length of the device. As with the embodiments described above, the nanowire channel region 702 can comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel region. Optionally, where the channel region 702 includes a crystalline silicon, the channel region can be formed to have <100> surface crystalline orientation relative to a long axis of the channel region.

In accordance with the present disclosure, the non-planar multigate memory transistor 700 of FIG. 7A can include a high work function gate electrode and a multi-layer charge-trapping region. FIG. 7B is a cross-sectional view of a portion of the non-planar memory transistor of FIG. 7A including a portion of the substrate 706, nanowire channel region 702 and the gate 712 illustrating a high work function gate electrode 714 and a multi-layer charge-trapping region 716 a-716 c. Referring to FIG. 7B, the gate 712 further includes a tunnel dielectric layer 718 overlying the nanowire channel region 702, and a blocking dielectric layer 720.

As with the embodiments described above, the high work function gate electrode 714 includes a doped polysilicon layer formed or deposited in a low pressure CVD process and having a thickness of from about 200 Å to about 2000 Å. The polysilicon layer of the high work function gate electrode 714 can be formed or grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane or BF₂, and is doped to a concentration or dose selected so that the minimum energy needed to remove an electron from the gate electrode is from at least about 4.8 eV to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 714 is doped to a concentration of from about 1e14 cm⁻² to about 1e16 cm⁻².

The multi-layer charge-trapping region 716 a-716 c includes at least one inner oxygen-rich first nitride layer 716 a comprising nitride closer to the tunnel dielectric layer 718, and an outer oxygen-lean second nitride layer 716 b overlying the oxygen-rich first nitride layer. Generally, the outer oxygen-lean second nitride layer 716 b comprises a silicon-rich, oxygen-lean nitride layer and comprises a majority of a charge traps distributed in the multi-layer charge-trapping region, while the oxygen-rich first nitride layer 716 a comprises an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the outer oxygen-lean second nitride layer to reduce the number of charge traps therein.

In some embodiments, such as that shown, the multi-layer charge-trapping region 716 further includes at least one thin, intermediate or anti-tunneling layer 716 c comprising a dielectric, such as an oxide, separating outer oxygen-lean second nitride layer 716 b from the oxygen-rich first nitride layer 716 a. The anti-tunneling layer 716 c substantially reduces the probability of electron charge that accumulates at the boundaries of outer oxygen-lean second nitride layer 716 b during programming from tunneling into the oxygen-rich first nitride layer 716 a, resulting in lower leakage current.

As with the embodiment described above, either or both of the oxygen-rich first nitride layer 716 a and the outer oxygen-lean second nitride layer 716 b can comprise silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N₂O/NH₃ and DCS/NH₃ gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. The second nitride layer of the multi-layer charge storing structure is then formed on the middle oxide layer. The outer oxygen-lean second nitride layer 716 b has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the oxygen-rich first nitride layer 716 a, and may also be formed or deposited by a CVD process using a process gas including DCS/NH₃ and N₂O/NH₃ gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer.

In those embodiments including an intermediate or anti-tunneling layer 716 c comprising oxide, the anti-tunneling layer can be formed by oxidation of the oxygen-rich first nitride layer 716 a, to a chosen depth using radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1000-1100 degrees Celsius using a single wafer tool, or 800-900 degrees Celsius using a batch reactor tool. A mixture of H₂ and O₂ gasses may be employed at a pressure of 300-500 Tor for a batch process, or 10-15 Tor using a single vapor tool, for a time of 1-2 minutes using a single wafer tool, or 30 min-1 hour using a batch process.

Finally, in those embodiments in which the blocking dielectric 720 comprises oxide, the oxide may be formed or deposited by any suitable means. In one embodiment the oxide of blocking dielectric layer 720 is a high temperature oxide deposited in a HTO CVD process. Alternatively, the blocking dielectric layer 720 or blocking oxide layer may be thermally grown, however it will be appreciated that in this embodiment the thickness of the outer oxygen-lean second nitride layer 716 b may need to be adjusted or increased as some of the top nitride will be effectively consumed or oxidized during the process of thermally growing the blocking oxide layer.

A suitable thickness for the oxygen-rich first nitride layer 716 a may be from about 30 Å to about 80 Å (with some variance permitted, for example ±10 A), of which about 5-20 Å may be consumed by radical oxidation to form the anti-tunneling layer 716 c. A suitable thickness for the outer oxygen-lean second nitride layer 716 b may be at least 30 Å. In certain embodiments, the outer oxygen-lean second nitride layer 716 b may be formed up to 70 Å thick, of which 30-70 Å may be consumed by radical oxidation to form the blocking dielectric layer 720. A ratio of thicknesses between the oxygen-rich first nitride layer 716 a and the outer oxygen-lean second nitride layer 716 b is approximately 1:1 in some embodiments, although other ratios are also possible.

In other embodiments, either or both of the outer oxygen-lean second nitride layer 716 b and the blocking dielectric layer 720 may comprise a high K dielectric. Suitable high K dielectrics include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y₂O₃.

FIG. 7C illustrates a cross-sectional view of a vertical string of non-planar multigate devices 700 of FIG. 7A arranged in a Bit-Cost Scalable or BiCS architecture 726. The architecture 726 consists of a vertical string or stack of non-planar multigate devices 700, where each device or cell includes a channel region 702 overlying the substrate 706, and connecting a source region and a drain region (not shown in this figure) of the memory transistor, and having a gate-all-around (GAA) structure in which the nanowire channel region 702 is enclosed on all sides by a gate 712. The BiCS architecture reduces number of critical lithography steps compared to a simple stacking of layers, leading to a reduced cost per memory bit.

In another embodiment, the memory transistor is or includes a non-planar device comprising a vertical nanowire channel region formed in or from a semiconducting material projecting above or from a number of conducting, semiconducting layers on a substrate. In one version of this embodiment, shown in cut-away in FIG. 8A, the memory transistor 800 comprises a vertical nanowire channel region 802 formed in a cylinder of semiconducting material connecting a source region 804 and drain region 806 of the device. The channel region 802 is surrounded by a tunnel dielectric layer 808, a multi-layer charge-trapping region 810, a blocking dielectric layer 812 and a high work function gate electrode 814 overlying the blocking dielectric layer to form a control gate of the memory transistor 800. The channel region 802 can include an annular region in an outer layer of a substantially solid cylinder of semiconducting material, or can include an annular layer formed over a cylinder of dielectric filler material. As with the horizontal nanowires described above, the channel region 802 can comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel region. Optionally, where the channel region 802 includes a crystalline silicon, the channel region can be formed to have <100> surface crystalline orientation relative to a long axis of the channel region.

As with the embodiments described above, the high work function gate electrode 814 includes a doped polysilicon layer formed or deposited in a low pressure CVD process and having a thickness of from about 200 Å to about 2000 Å. The polysilicon layer of the high work function gate electrode 814 can be formed or grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane or BF₂, and is doped to a concentration or dose selected so that the minimum energy needed to remove an electron from the gate electrode is from at least about 4.8 eV to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 814 is doped to a concentration of from about 1e14 cm⁻² to about 1e16 cm⁻².

In some embodiments, such as that shown in FIG. 8B, the multi-layer charge-trapping region 810 includes at least an inner or oxygen-rich first nitride layer 810 a closest to the tunnel dielectric layer 808, and an outer or oxygen-lean second nitride layer 810 b. Optionally, as in the embodiment shown, the oxygen-rich first nitride layer 810 a and the oxygen-lean second nitride layer 810 b are separated by an intermediate oxide or anti-tunneling layer 810 c comprising oxide.

Either or both of the oxygen-rich first nitride layer 810 a and the oxygen-lean second nitride layer 810 b can comprise silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N₂O/NH₃ and DCS/NH₃ gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer.

Finally, either or both of the oxygen-lean second nitride layer 810 b and the blocking dielectric layer 812 may comprise a high K dielectric, such as HfSiON, HfSiO, HfO, ZrSiON, ZrSiO, ZrO, or Y₂O₃.

A suitable thickness for the oxygen-rich first nitride layer 810 a may be from about 30 Å to about 80 Å (with some variance permitted, for example ±10 A), of which about 5-20 Å may be consumed by radical oxidation to form the anti-tunneling layer 820. A suitable thickness for the oxygen-lean second nitride layer 810 b may be at least 30 Å, and a suitable thickness for the blocking dielectric layer 812 may be from about 30-70 Å.

The memory transistor 800 of FIG. 8A can be made using either a gate first or a gate last scheme. FIGS. 9A-F illustrate a gate first scheme for fabricating the non-planar multigate device of FIG. 8A. FIGS. 10A-F illustrate a gate last scheme for fabricating the non-planar multigate device of FIG. 8A.

Referring to FIG. 9A, in a gate first scheme a first or lower dielectric layer 902, such as an oxide, is formed over a first, doped diffusion region 904, such as a source region or a drain region, in a substrate 906. A high work function gate electrode 908 is formed over the first dielectric layer 902 to form a control gate of the device, and a second or upper dielectric layer 910 formed thereover. As with embodiments described above, the high work function gate electrode 908 can be formed by depositing and/or doping polysilicon layer having a thickness of from about 200 Å to about 2000 Å and a dopant concentration of from about 1e14 cm⁻² to about 1e16 cm⁻² so that the minimum energy needed to remove an electron from the gate electrode is from at least about 4.8 eV to about 5.3 eV. The polysilicon layer can be deposited in a low pressure CVD process as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane or BF₂, or can be doped using an ion implantation process following deposition.

The first and second dielectric layers 902, 910, can be deposited by CVD, radical oxidation or be formed by oxidation of a portion of the underlying layer or substrate. Generally the thickness of the high work function gate electrode 908 is from about 40-50 Å, and the first and second dielectric layers 902, 910, from about 20-80 Å.

Referring to FIG. 9B, a first opening 912 is etched through the overlying high work function gate electrode 908, and the first and second dielectric layers 902, 910, to the diffusion region 904 in the substrate 906. Next, layers of a tunneling oxide 914, charge-trapping region 916, and blocking dielectric 918 are sequentially deposited in the opening and the surface of the upper dielectric layer 910 planarized to yield the intermediate structure shown in FIG. 9C.

Although not shown, it will be understood that as in the embodiments described above the charge-trapping region 916 can include a multi-layer charge-trapping region comprising at least one lower or oxygen-rich first nitride layer closer to the tunnel dielectric layer 914, and an upper or oxygen-lean second nitride layer overlying the oxygen-rich first nitride layer. Generally, the oxygen-lean second nitride layer comprises a silicon-rich, oxygen-lean nitride layer and comprises a majority of a charge traps distributed in the multi-layer charge-trapping region, while the oxygen-rich first nitride layer comprises an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the oxygen-lean second nitride layer to reduce the number of charge traps therein. In some embodiments, the multi-layer charge-trapping region 916 further includes at least one thin, intermediate or anti-tunneling layer comprising a dielectric, such as an oxide, separating the oxygen-lean second nitride layer from the oxygen-rich first nitride layer.

Next, a second or channel region opening 920 is anisotropically etched through tunneling oxide 914, charge-trapping region 916, and blocking dielectric 918, FIG. 9D. Referring to FIG. 9E, a semiconducting material 922 is deposited in the channel region opening to form a vertical channel region 924 therein. The vertical channel region 924 can include an annular region in an outer layer of a substantially solid cylinder of semiconducting material, or, as shown in FIG. 9E, can include a separate, layer semiconducting material 922 surrounding a cylinder of dielectric filler material 926.

Referring to FIG. 9F, the surface of the upper dielectric layer 910 is planarized and a layer of semiconducting material 928 including a second, doped diffusion region 930, such as a source region or a drain region, formed therein deposited over the upper dielectric layer to form the device shown.

Referring to FIG. 10A, in a gate last scheme a dielectric layer 1002, such as an oxide, is formed over a sacrificial layer 1004 on a surface on a substrate 1006, an opening etched through the dielectric and sacrificial layers and a vertical channel region 1008 formed therein. As with embodiments described above, the vertical channel region 1008 can include an annular region in an outer layer of a substantially solid cylinder of semiconducting material 1010, such as polycrystalline or monocrystalline silicon, or can include a separate, layer semiconducting material surrounding a cylinder of dielectric filler material (not shown). The dielectric layer 1002 can comprise any suitable dielectric material, such as a silicon oxide, capable of electrically isolating the subsequently formed high work function gate electrode of the memory transistor 800 from an overlying electrically active layer or another memory transistor.

Referring to FIG. 10B, a second opening 1012 is etched through the etched through the dielectric and sacrificial layers 1002, 1004, to the substrate 1006, and the sacrificial layer 1004 at least partially etched or removed. The sacrificial layer 1004 can comprise any suitable material that can be etched or removed with high selectivity relative to the material of the dielectric layer 1002, substrate 1006 and vertical channel region 1008. In one embodiment the sacrificial layer 1004 comprises an oxide that can be removed by Buffered Oxide Etch (BOE etch).

Referring to FIG. 10C and 10D, a tunnel dielectric layer 1014, a multi-layer charge-trapping region 1016A-C, and a blocking dielectric layer 1018 are sequentially deposited in the opening, and the surface of the dielectric layer 1002 planarized to yield the intermediate structure shown in FIG. 10C. As in the embodiments described above, the multi-layer charge trapping layer 1016A-C is a split multi-layer charge trapping layer including at least an inner oxygen-rich first nitride layer 1016A closest to the tunnel dielectric layer 1014, and an outer, oxygen-lean second nitride layer 1016B. Optionally, the first and second charge trapping layers can be separated by an intermediate oxide or anti-tunneling layer 1016C.

Next, a high work function gate electrode 1022 is deposited into the second opening 1012 and the surface of the upper dielectric layer 1002 planarized to yield the intermediate structure illustrated in FIG. 10E. As with the embodiments described above, the high work function gate electrode 1022 includes a doped polysilicon layer having a dopant concentration of from about 1e14 cm⁻² to about 1e16 cm⁻² so that the minimum energy needed to remove an electron from the gate electrode is from at least about 4.8 eV to about 5.3 eV. The polysilicon layer of the high work function gate electrode 1022 is grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane or BF₂, to the CVD process. Finally, an opening 1024 is etched through the gate layer 1022 to form control gates of separate memory devices 1026A and 1026B.

The foregoing description of specific embodiments and examples of the invention have been presented for the purpose of illustration and description, and although the invention has been described and illustrated by certain of the preceding examples, it is not to be construed as being limited thereby. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications, improvements and variations within the scope of the invention are possible in light of the above teaching. It is intended that the scope of the invention encompass the generic area as herein disclosed, and by the claims appended hereto and their equivalents. The scope of the present invention is defined by the claims, which includes known equivalents and unforeseeable equivalents at the time of filing of this application. 

What is claimed is:
 1. A memory device, comprising: a gate structure including a gate electrode comprising a polysilicon layer; a channel positioned between and electrically connecting a first diffusion region and a second diffusion region; and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel, wherein the multi-layer charge trapping layer comprises a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. 